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STORE (19 WORDS K2 WORDS X6 BITS) X6 BITS) INTERFACE CIRCUITS AND CLOCK AND MULTIPLEXER INTER FACE CIRCUIT TEMAX VAX COMPARATOR T < MAX 62 TO. A plurality of comparators for comparing the input signal to different reference 2(b) and 2(c) are circuit diagrams of a non-inverting delay stage and. No. , Int. Cl. G06F 9/30 ; 12/00 U.S. CI. assignor to International a plurality of comparator circuits wherein each of said plurality Business. INSTAFOREX BEAUTY CONTEST SCANDAL Please mind that has special applications the Connection Properties implemented: Google Keep helps manage computers. Support ID - Stack Overflow - it is easy Down and No-Flows connect to the Remote PC and. The garage to.

Typically, the sampling mode is performed or used before the comparison mode. To facilitate presentation, however, the comparison mode is described first. Note that because charge leakage can discharge the offset stored on the sampling capacitors AZ 1 and AZ 2 , the comparator cannot stay in the comparison mode for too long of a time period, and is switched back to the sampling mode to sample the offset again.

In the comparison mode of operation, the switches 25 - 1 through 25 - 10 are opened. In this mode, the circuitry of the comparator 10 in FIG. Thus, the comparator 10 compares the values of the inputs signals applied to its differential input, and provides an output signal at its differential output that represents the results of the comparison. In the other mode, i. During this mode, fixed or relatively or nearly fixed, in a real-world, practical implementation DC voltages vcm 1 and vcm 2 are used, as shown in FIG.

More specifically, the fixed DC voltages vcm 1 and vcm 2 are used to set the DC operating points of the various stages of the comparator The differential input of the comparator 10 is coupled to the fixed DC voltage vcm 1 through switches 25 - 8 to 25 - The inputs of the comparator are thus shorted together. As a result, any offset in stage 1 15 - 1 will appear at the output of the first stage, i. If the circuit were ideal and no offset were present in stage 1 , the capacitor AZ 1 would store the common mode output on its left plate, and the voltage vcm 2 on the right plate.

So when the comparator goes into the comparison mode, the second stage would see the voltage vcm 2 as its input common mode. Since the circuit is not ideal because of the limitations of a real-life, physical implementation, and an offset will show at the output of the first stage, it will be stored together with the other signals on the capacitors AZ 1.

The switches 25 - 4 and 25 - 7 create a feedback loop that can be unstable but the switches 25 - 5 and 25 - 6 couple a Miller capacitor and a nulling resistor that will force the loop into a stable state. Thus, the switches 25 - 5 and 25 - 6 should close before the switches 25 - 4 and 25 - 7 , and they should be opened after those switches. As a result of closing all of the switches 25 - 1 to 25 - 10 , the inputs of the second stage stage 15 - 2 are also shorted together.

Any offset in the second stage will therefore appear at the output of the second stage, i. Through the operation of the switches 25 - 4 and 25 - 7 , the outputs of the fourth stage 15 - 4 are coupled to the inputs of the third stage 15 - 3 in a common-mode feedback path. As a result, any offset of the third and fourth stages will be stored on the capacitors AZ 2 more specifically, on the right plates of the capacitors AZ 2. The common-mode feedback path will also set or fix the DC operating points for the third and fourth stages.

The outputs of Stage 4 are shorted to the inputs of Stage 3 in a common mode feedback path which will allow the offset of stages 3 and 4 to be stored at the right plate of the capacitor AZ 2. The resulting offset error at the output of stage 4 will roughly be equal to the offset of the third stage according to the following equation:. At the conclusion of the sampling mode, i. The comparator 10 will then be ready for operation in the comparison mode, as described above.

When opening a switch, the control signal on the switches can couple to the other nodes of the switch, thereby causing a charge injection error, which can introduce some offset as well. To avoid this outcome, different clock phases are used to open the switches in a sequence that will reduce the offset due to this charge injection as much as possible. The goal is to cancel as much offset as possible, store what cannot be canceled, so that if any offset is left over, it should have minimum effect.

The sequence starts by first opening the switches 25 - 8 through 25 - 10 coupled to the inputs of the first stage. These switches are controlled by the DO clock signal. To reduce the charge injection even further, a combination of single ended switches switch 25 - 8 and switch 25 - 10 and differential switch switch 25 - 9 are used instead of only using single ended switches.

The single ended switches will open first, causing charge injection at the inputs of the first stage. But since the differential switch is still closed, the charge will get redistributed and cause the same voltage on both nodes of the differential switch, thus they will not produce any offset due to charge injection when they are opened.

Next the differential switch 25 - 9 opens. The differential switch is usually a smaller switch, and so it will inject a smaller and almost equal amount of charge on both of its nodes the inputs of the first stage.

Single ended switches 25 - 1 and 25 - 3 open first, and their charge injection offset will get canceled by the differential switch 25 - 2. Thereafter, the differential switch 25 - 2 opens, and any offset due to its charge injection will be seen at the input of the second stage, and will get stored and canceled by the capacitors AZ 2. The last clock phase corresponds to the clock signal Since any charge injected offset here will not get amplified, and since no more phases in the comparator are left, this phase's charge injected offset is not canceled and will add to the final offset error of the comparator When this offset is referred back to the input, it will be divided by the gains of pregain stages 1 and 2 , and will become effectively relatively small.

For the clock signal 12 , switches 25 - 4 and 25 - 7 open first in order to interrupt the feedback path before opening the switches 25 - 5 and 25 - 6. Doing so avoids instability if the compensation paths the Miller capacitors and nulling resistors are uncoupled while the feedback is still present.

Comparators according to various embodiments may be used in a variety of applications, as desired. Without limitation, some applications are described below. A fed back sample of the output voltage of the regulator is provided to the ADJ input of the regulator. The output of the comparator 10 is used to control a switch, typically a transistor M. The transistor is used to charge the output capacitor C OUT when the voltage across the capacitor drops in order to keep the voltage of the regulator relatively close to the reference voltage.

The details of the topology and operation of the switching regulator depend on design and specification details, such as the magnitudes of the input and output voltages, etc. The output signal of the amplifier 82 feeds the inverting input of the comparator 10 , whereas a threshold voltage VTH drives the non-inverting input of the comparator The comparator 10 compares the two input signals.

The results of the comparison are provided to the control circuitry The control circuitry may further process the results of the comparison, control various circuitry, etc. The low offset of the comparator 10 , owing to the offset cancellation described above, will translate to lower offset error in the temperature sensor The control system includes a transducer 85 that converts a physical quantity e. The output of the transducer 85 is coupled to the inverting input of the comparator A reference voltage VREF drives the non-inverting input of the comparator The comparator 10 compares the output signal of the transducer 85 to the reference voltage.

The output voltage of the comparator 10 is provided to the control circuitry The control circuitry 90 may perform various processes on the output signal of the comparator 10 based on or derived from the output signal of the comparator Examples include proportional control, integral control, differential control, proportional-integral-differential control, etc. One or more outputs of the control circuitry 90 drive the loop circuitry 95 , which generates a physical quantity in response to the signals from the control circuitry Thus, a control feedback loop is established around circuitry that includes the comparator IC includes a number of blocks e.

In exemplary embodiments, link may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements e. IC may include link coupled to one or more processors , clock circuitry , and power management circuitry or power management unit PMU In some embodiments, processor s may include circuitry or blocks for providing information processing or data processing or computing functions, such as central-processing units CPUs , arithmetic-logic units ALUs , and the like.

In some embodiments, in addition, or as an alternative, processor s may include one or more DSPs. The DSPs may provide a variety of signal processing functions, such as arithmetic functions, filtering, delay blocks, and the like, as desired. Clock circuitry may generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC Clock circuitry may also control the timing of operations that use link , as desired.

In some embodiments, clock circuitry may provide one or more clock signals via link to other blocks in IC In some embodiments, PMU may reduce an apparatus's e. Further, PMU may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the foregoing in response to a transition from an inactive state to an active state including, without limitation, when processor s make a transition from a low-power or idle or sleep state to a normal operating state.

Link may couple to one or more circuits through serial interface Through serial interface , one or more circuits or blocks coupled to link may communicate with circuits Circuits may communicate using one or more serial protocols, e. In exemplary embodiments, peripherals may include a variety of circuitry, blocks, and the like.

Note that in some embodiments, some peripherals may be external to IC Examples include keypads, speakers, and the like. In some embodiments, such peripherals may be external to IC , as described above. Link may couple to analog circuitry via data converter s ADC s A receive analog signal s from analog circuitry , and convert the analog signal s to a digital format, which they communicate to one or more blocks coupled to link Conversely, DAC s B receive digital signal s from one or more blocks coupled to link , and convert the digital signal s to analog format, which they communicate to analog circuitry Examples include comparators such as the comparator 10 described above , sensors, transducers, and the like, as person of ordinary skill in the art will understand.

In some embodiments, analog circuitry may communicate with circuitry external to IC to form more complex systems, sub-systems, control blocks or systems, feedback systems, and information processing blocks, as desired. Control circuitry couples to link In some embodiments, control circuitry also receives status information or signals from various blocks coupled to link In addition, in some embodiments, control circuitry facilitates or controls or supervises communication or cooperation between various blocks coupled to link In some embodiments, control circuitry may initiate or respond to a reset operation or signal.

The reset operation may cause a reset of one or more blocks coupled to link , of IC , etc. For example, control circuitry may cause PMU or other circuitry in IC to reset to an initial or known state. In exemplary embodiments, control circuitry may include a variety of types and blocks of circuitry.

In some embodiments, control circuitry may include logic circuitry, finite-state machines FSMs , or other circuitry to perform operations such as the operations described above. Communication circuitry couples to link and also to circuitry or blocks not shown external to IC Through communication circuitry , various blocks coupled to link or IC , generally can communicate with the external circuitry or blocks not shown via one or more communication protocols.

Examples of communications include USB, Ethernet, and the like. In exemplary embodiments, other communication protocols may be used, depending on factors such as design or performance specifications for a given application, as person of ordinary skill in the art will understand.

As noted, memory circuit couples to link Memory circuit provides storage for various information or data in IC , such as operands, flags, data, instructions, and the like, as persons of ordinary skill in the art will understand. A direct memory access DMA arrangement not shown allows increased performance of memory operations in some situations.

More specifically, DMA not shown provides a mechanism for performing memory read and write operations directly between the source or destination of the data and memory circuit , rather than through blocks such as processor s Memory circuit may include a variety of memory circuits or blocks. In the embodiment shown, memory circuit includes non-volatile NV memory In addition, or instead, memory circuit may include volatile memory not shown , such as random access memory RAM.

NV memory may be used for storing information related to performance, control, or configuration of one or more blocks in IC For example, NV memory may store configuration information or firmware for various blocks or circuits in IC Comparators according to various embodiments may be used in a variety of circuits or blocks in IC As another example, in some embodiments, comparator s may be used in PMU , for instance, to determine whether thresholds e.

Comparator s may be used in other blocks or additional blocks of IC , as desired, and such use is contemplated, as persons of ordinary skill in the art will understand. Various circuits and blocks described above and used in exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. In addition, digital circuitry or mixed-signal circuitry or both may be included. The digital circuitry may include circuit elements or blocks such as gates, digital multiplexers MUXs , latches, flip-flops, registers, finite state machines FSMs , processors, programmable logic e.

The choice of circuitry for a given implementation depends on a variety of factors, as persons of ordinary skill in the art will understand. Such factors include design specifications, performance specifications, cost, IC or device area, available technology, such as semiconductor fabrication technology , target markets, target end-users, etc.

Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown might depict mainly the conceptual functions and signal flow. Persons of skill in the art would readily recognize that if the output of the edge detection logic is in the form of "negative logic," i. In these implementations and , rising edge detection logic is provided by inverting the other input of the gate in the respective falling edge detection logic and Specifically, in FIG.

Thus, the output of AND gate is high only when both inputs are high, that is, when the input to the non-inverting delay stage a is currently low and inverted by inverter and when the output of the non-inverting delay stage a is currently high. Moreover, in FIG. Thus, the output of NOR gate is high only when both inputs are low, that is, when the output to the non-inverting delay stage a is currently high and inverted by inverter and when the input of the non-inverting delay stage a is currently low.

Specifically, edge detection logic comprises an exclusive OR XOR gate , which outputs a high level only if the level of one of the inputs is different from the other, that is, when either edge, rising or falling, is currently being delayed by delay stage a. If, on the other hand, the delay stages a and b are implemented by inverting delay stages , then the edge detection logic may be implemented according to the configurations depicted in FIGS.

The AND gate outputs a high level only if both inputs are high, that is, if the input to inverting delay stage a is high and the inverted output of inverting delay stage a is high, which occurs when there is a falling edge in the pulse currently delayed by delay state a.

The multi-level quantizer illustrated in FIG. For example, an analog signal varying over time, such as the signal depicted in the graph of FIG. In response, each comparator compares the applied input analog signal to a different reference potential and produces therefrom a digital pulse based on a comparison of the voltage if the input analog signal exceeds the voltage of the reference potential. There are a variety of approaches to producing the pulse based on the comparison.

According to one possible approach illustrated in FIG. According to another approach, however, the comparators may be configured to output a pulse only for the time in which the input voltage is within a small potential window, e. In the first approach, since the reference potentials are produced from a voltage divider , comparator C1 generates a pulse only when the analog signal attains a relatively high voltage level, but comparator C4 , on the other hand, generates a pulse when the analog signal reaches a lower voltage level.

In this configuration, an upper level comparator, e. The pulses produced from the comparators are applied to a corresponding delay line and are repeatedly delayed for a common delay period by successive delay stages in the delay line. The edge detection logic at various stages in the delay line output a signal indicative of the presence of an edge of a pulse in the delay line at the delay stage.

For example, in FIG. Thus, each delay line through its edge detection logic outputs signals indicative of detected edges at a delay stage corresponding to transitions of the input signal across a reference potential. Earlier transitions propagate further down in the delay line than later transitions. Accordingly, the edge detection signals at various stages in the delay line provide time-based information of the behavior of the input analog signal. Therefore, each delay line provides a snapshot of time-based information for transitions across a particular reference potential, and the use of a plurality delay lines for a plurality reference potentials provides amplitude information for the input signal.

Consequently, the multi-level quantizer can be monitored by pattern detection logic at a point in time and thus detect an incoming signal. As evident from the graph, every rising edge detected within a delay line indicates an upward transition of input signal across the reference potential of the corresponding comparator.

Moreover, rising edge detections at subsequent delay stages imply, by an assumption of continuity, that there was a downward transition across the reference potential in the input signal. Therefore, the information about the detected rising edges is sufficient to reconstruct the analog input signal within the precision in the amplitude domain afforded by the number of comparators. Likewise, information about detected falling edges or both rising and falling edges combined can be used to reconstruct the input signal.

Consequently, multi-level quantizer can be used to implement a generic demodulator. Greater precision in the amplitude domain may be achieved by adding more delay lines in parallel in conjunction with additional comparators for comparing the input signal to additional reference potentials. Greater precision in the timing domain may be attained by using or calibrating the delay stages to a shorter delay period. Another approach in obtaining greater timing precision is to detect both upward and downward transitions in the input signal, e.

Consequently, a scalable signal detector or demodulator is advantageously attained by the present invention. Occasionally, input signals are corrupted with noise and tend to have more "jitter" than clean signals. Jitter manifests itself in the delay lines by causing an edge detection signal to be generated at a delay stage or two before or after the delay stage at which the edge would have been detected in a clean signal.

According to one embodiment of the present invention, the random effects of jitter of a periodic signal are counted and averaged out. The voltage divider includes taps between the resistive elements , which are coupled to corresponding comparators , , , and for providing respective reference potentials thereto. Each comparator is configured to receive an analog input signal from node V in and compare the voltage of the analog input signal to the voltage of the reference potential.

In response, each comparator generates a pulse based on the voltage comparisons. The output of each comparator is coupled to a corresponding delay line , , , and for repeatedly delaying the pulses from the comparators As explained in more detail hereinafter, each delay line is configured to detect edges of the pulses and count the detected edges in response to a master clock signal. Pattern matching logic may be coupled to various outputs of the delay lines to access the edge counts for use in detecting a signal.

The exemplary delay line includes a chain of serially coupled delay stages with edge detection logic coupled to an input and output of a delay stage In the example, the exemplary delay line is implemented with non-inverting delay stages and rising edge detection logic, but it is evident that the delay line may be implemented with other kinds of delay stage stages, for example inverting delay stages, and various kinds and species of edge detection logic, for example falling edge detection logic.

The output of the edge detection logic is coupled to a counter , which is configured to increment when the edge detection logic indicates a detected edge and a clock signal asserted on a master clock line. The master clock signal may be synchronized to the periodic input signal, e. Thus, the output pulses of each comparator are roughly periodic as shown in FIG.

For example, comparator C3 over the course of eight master clock periods may generate pulses that cause the fifth delay stage to increment a corresponding counter twice, the sixth delay stage three times, and the seventh delay stage once. Accordingly, the counters will tend to accumulate edges at the location of transitions in the input signals. If there is jitter in the periodic input signal, then adjacent counters near the location of the edge will also contain a number of counts.

The combination of these adjacent counters can be viewed as a "histogram" of detected edges. In the example as illustrated in FIG. These histograms associated with transitions in the input signal across a reference potential provide valuable information about the quality of the input signal.

This information may be used by other components in a communications system to make intelligent decisions concerning the operation of the system. For example, the observation of excessive according to some empirically predefined threshold counts in an adjacent counter may indicate that the overall signal to noise ratio in the channel of the input signal has degraded. The system may respond by such actions as boosting the transmission power or increasing the level of error correction in signal detection.

As explained hereinabove, some implementations of multi-level quantizers and include a plurality of comparators and associated delay lines for capturing information contained in the amplitude components of the input signal. Certain kinds of modulation, for example frequency modulation FM or frequency shift keying FSK , on the other hand, do not encode information in the amplitude of the transmitted signal but in changes in the timing of the signal.

In this case, a single delay line, such as delay line or , suffices for capturing the timing information of the signal. If the voltage swing of the input signal already matches the voltage range of the delay line e.

On the other hand, if the voltage swings do not match, then a single comparator with an appropriately predefined reference voltage may be used to convert the logical levels of the input signal. While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

What is claimed is: 1. A circuit for detecting a digital signal, comprising: a plurality of delay stages coupled in series;. The circuit of claim 1, wherein the prescribed characteristic of the digital signal is an edge in the digital signal. The circuit of claim 1, wherein the delay stage includes a non-inverting delay stage. The circuit of claim 3, wherein the edge detection logic includes an XOR gate coupled to the input and output of the non-inverting delay stage. The circuit of claim 3, wherein the edge detection logic includes an inverter coupled to the output of the non-inverting delay stage.

The circuit of claim 5, wherein the edge detection logic further includes an AND gate coupled to an output of the inverter and the input of the non-inverting delay stage. The circuit of claim 5, wherein the edge detection logic further includes a NOR gate coupled to an output of the inverter and the input of the non-inverting delay stage.

The circuit of claim 3, wherein the edge detection logic includes an inverter coupled to the input of the non-inverting delay stage. The circuit of claim 8, wherein the edge detection logic further includes an AND gate coupled to an output of the inverter and the output of the non-inverting delay stage. The circuit of claim 8, wherein the edge detection logic further includes a NOR gate coupled to an output of the inverter and the output of the non-inverting delay stage.

The circuit of claim 3, wherein the non-inverting delay stage includes a pair of inverting delay stages coupled in series. The circuit of claim 1, wherein the delay stage includes an inverting delay stage. The circuit of claim 12, wherein the edge detection logic includes an XNOR gate coupled to the input of the inverting delay stage and the output of the inverting delay stage. The circuit of claim 12, wherein the edge detection logic further includes an AND gate coupled to the output of the inverting delay stage and the input of the inverting delay stage.

The circuit of claim 12, wherein the edge detection logic further includes a NOR gate coupled to the output of the inverting delay stage and the input of the inverting delay stage. The circuit of claim 1, wherein the edge detection logic includes an inverter coupled to the input of the delay stage. The circuit of claim 16, wherein the edge detection logic further includes an AND gate coupled to an output of the inverter and the output of the delay stage.

The circuit of claim 16, wherein the edge detection logic further includes a NOR gate coupled to an output of the inverter and the output of the delay stage. The circuit of claim 1, wherein each delay stage is configured to receive a calibration signal and in response vary a delay period of said stage. A circuit for detecting an input signal, comprising: one or more comparators for comparing the input signal with a respective reference potential and producing therefrom pulses indicative of a comparison of the input signal and the respective reference potential; and.

The circuit of claim 20, wherein the detection logic includes rising edge detection logic. The circuit of claim 20, wherein the detection logic includes falling edge detection logic. The circuit of claim 20, further comprising a plurality of counters responsive to a clock signal, coupled to the one or more digital delay lines, and configured to count a number of the prescribed characteristics.

The circuit of claim 20, further comprising a voltage divider including a serially coupled chain of resistive elements between a supply potential source and a ground potential source for supplying the plurality of respective reference potentials to the respective comparators. The circuit of claim 24, wherein the resistive elements include a resistor. The circuit of claim 24, wherein the resistive elements include a biased semiconductor junction.

The circuit of claim 20, further comprising means for supplying the plurality of respective reference potentials to the respective comparators. A method of detecting a signal, comprising the steps of: comparing the signal to a plurality of reference potentials to produce therefrom a plurality of corresponding pulses;.

The method of claim 28, wherein the step of detecting a prescribed characteristic in the plurality of delayed pulses includes the step of detecting edges in the plurality of delayed pulses. The method of claim 29, wherein the step of detecting edges includes the step of detecting falling edges in the plurality of delayed pulses. The method of claim 29, wherein the step of detecting edges includes the step of detecting rising edges in the plurality of delayed pulses.

The method of claim 29, further comprising the step of counting the detected edges. The method of claim 32, further comprising the step of synchronizing a clock signal to a period of the signal, wherein the step of counting the detected edges includes the step of counting the detected edges based on the synchronized clock signal.

The method of claim 28, further comprising the step of supplying the plurality of reference potentials. The method of claim 28, further comprising the step of calibrating the common delay period. Signal detection circuit using a plurality of delay stages with edge detection logic.

USA en. Semiconductor device including a control signal generation circuit allowing reduction in size. USB1 en. Optical cross-connect switching system with bridging, test access and redundancy. Method and apparatus for optical to electrical to optical conversion in an optical cross-connect switch.

Method and apparatus for signaling between an optical cross-connect switch and attached network equipment.

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